ADSP-21160MKB-80

FEATURES

100 MHz (10 ns) core instruction rate (ADSP-21160N)

Single-cycle instruction execution, including SIMD operations in both computational units

Dual data address generators (DAGs) with modulo and bitreverse addressing

Zero-overhead looping and single-cycle loop setup, providing efficient program sequencing

IEEE 1149.1 JTAG standard Test Access Port and on-chip emulation

400-ball 27 mm × 27 mm PBGA package

Available in lead-free (RoHS compliant) package 200 million fixed-point MACs sustained performance (ADSP-21160N)

Single-instruction, multiple-data (SIMD) 

 GENERAL DESCRIPTION

 The ADSP-21160x SHARC® DSP family has two members: ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabricated in a 0.25 micron CMOS process. The ADSP-21160N is fabricated in a 0.18 micron CMOS process. The ADSP-21160N offers higher performance and lower power consumption than the ADSP-21160M. Easing portability, the ADSP-21160x is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (single instruction, single data) mode. To take advantage of the processor’s SIMD (singleinstruction, multiple-data) capability, some code changes are needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160x includes a core running up to 100 MHz, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.