NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR.Widebus, EPIC, UBT are trademarks of Texas Instruments.
Texas InstrumentsSN74ALVCH162601DLRThis 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH162601DLR combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
The B-port outputs include equivalent 26- series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162601DLR is characterized for operation from –0°C to 85°C.
類型 | 描述 | 全選 |
---|---|---|
系列 | 74ALVCH | |
包裝 | 卷帶(TR) | |
產品狀態 | 在售 | |
邏輯類型 | 通用總線收發器 | |
電路數 | 18 位 | |
電流 - 輸出高、低 | 24mA,24mA;12mA,12mA | |
電壓 - 供電 | 1.65V ~ 3.6V | |
工作温度 | -40°C ~ 85°C | |
安裝類型 | 表面貼裝型 | |
封裝/外殼 | 56-BSSOP(0.295",7.50mm 寬) | |
供應商器件封裝 | 56-SSOP |
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