The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz.
TotalCMOS Design Technique for Fast Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution, both in process technology and design technique. These CPLDs employ a cascade of CMOS gates to implement their sum of products, instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx CPLDs to offer devices that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance.
TYPE | DESCRIPTION | Select all |
---|---|---|
Package / Case | 100-TQFP | |
Programmable | Not Verified | |
Supplier Device Package | 100-VQFP (14x14) | |
Programmable Type | In System Programmable (min 1K program/erase cycles) | |
Delay Time tpd(1) Max | 5.5 ns | |
Voltage Supply - Internal | 3V ~ 3.6V | |
Number of Logic Elements/Blocks | 4 | |
Number of Macrocells | 64 | |
Number of Gates | 1500 | |
Number of I/O | 68 | |
Series | CoolRunner XPLA3 | |
Operating Temperature | 0°C ~ 70°C (TA) | |
Package | Tray | |
Mounting Type | Surface Mount | |
Product Status | Active |
AMD
AMD stands as a preeminent purveyor of All Programmable Field-Programmable Gate Arrays (FPGAs), System-on-Chips (SoCs), Multiprocessor SoCs (MPSoCs), and Three-Dimensional Integrated Circuits (3D ICs). Notably, AMD confers singular prowess in facilitating software-defined and hardware-optimized applications, thus propelling progress across domains like Cloud Computing, 5G Wireless, Embedded Vision, and Industrial Internet of Things (IoT).
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