AD567KD/+

Microprocessor compatibility is achieved by the on-chip double-buffered latch. The design of the input latch allows direct interface to 4-, 8-, 12-, or 16-bit buses. The 12 bits of data from the first rank of latches can then be transferred the second rank, avoiding generations of spurious analog output values. The latch responds to the strobe pulses as short as 100 ns, allowing use with the fastest available microprocessors.

The functional completeness and high performance in the AD567KD results from a combination of advanced switch design, high speed bipolar manufacturing process, and the proven laser wafer-trimming (LWT) technology. The AD567KD is trimmed at the wafer level and is specified to ±1/4 LSB maximum linearity error (K grade) at 25°C and ±1/2 LSB at the full operating temperature range.

The subsurface (buried) Zenor diode on the chip provides a low-noise voltage reference which has long term stability and temperature drift characteristics comparable to the best discrete reference diodes. The laser trimming process which provides the excellent linearity is also used to trim both the absolute value of the reference as well as its temperature coefficient. The AD567KD is thus well suited for wide temperature range performance with ±1/2 LSB maximum linearity error and guaranteed monotonicity over the full temperature range. Typical full scale gain T.C. is 10 ppm/°C.

The AD567KD is available in three performance grades. The AD567J and K are specified for use over the 0 to 70°C temperature range and are available in either 28-pin hermetically sealed, ceramic DIP or a 28-pin molded plastic DIP (N Package). The AD567S is specified for the -55°C to +125°C range and is available in the ceramic package.

Data Sheet, Rev. A, 1/83

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