Texas Instruments
德州仪器 (TI) 是一家开发模拟 IC 和嵌入式处理器的全球半导体设计和制造公司。 通过聘用世界上最聪明的人才,TI 创造了塑造技术未来的创新。 今天,TI 正在帮助超过 100,000 家客户改变未来。
查看所有产品从 Texas InstrumentsData sheet acquired from Harris Semiconductor
DescriptionThe device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3 following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE\ input low.
All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.
Data sheet acquired from Harris Semiconductor
DescriptionThe device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3 following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE\ input low.
All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.
类型 | 描述 | 全选 |
---|---|---|
系列 | 74HC | |
包装 | 卷带(TR) | |
产品状态 | 在售 | |
逻辑类型 | 双向寄存器 | |
输出类型 | 补充型 | |
元件数 | 1 | |
每个元件位数 | 4 | |
功能 | 通用 | |
电压 - 供电 | 2V ~ 6V | |
工作温度 | -55°C ~ 125°C | |
安装类型 | 表面贴装型 | |
封装/外壳 | 16-TSSOP(0.173",4.40mm 宽) | |
供应商器件封装 | 16-TSSOP |
Texas Instruments
德州仪器 (TI) 是一家开发模拟 IC 和嵌入式处理器的全球半导体设计和制造公司。 通过聘用世界上最聪明的人才,TI 创造了塑造技术未来的创新。 今天,TI 正在帮助超过 100,000 家客户改变未来。
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