CY7C4245-10AXCT

CY7C4245-10AXCT Features

CY7C4245-10AXCT Functional Description

■ High speed, low power, first-in first-out (FIFO) memories■ 64 x 18 (CY7C4425)■ 256 x 18 (CY7C4205)■ 512 x 18 (CY7C4215)■ 1K x 18 (CY7C4225)■ 2K x 18 (CY7C4235)■ 4K x 18 (CY7C4245)■ High speed 100 MHz operation (10 ns read/write cycle time)■ Low power (ICC = 45 mA)■ Fully asynchronous and simultaneous read and write operation■ Empty, Full, Half Full, and Programmable Almost Empty/AlmostFull status flags■ TTL compatible■ Retransmit function■ Output Enable (OE) pin■ Independent read and write enable pins■ Center power and ground for reduced noise■ Supports free running 50% duty cycle clock inputs■ Width Expansion Capability■ Depth Expansion Capability■ Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and68-pin PLCCThe CY7C42X5 are high speed, low power, first-in first-out(FIFO) memories with clocked read and write interfaces. All are18 bits wide and are pin/functionally compatible to IDT722X5.The CY7C42X5 can be cascaded to increase FIFO depth.Programmable features include Almost Full/Almost Empty flags.These FIFOs provide solutions for a wide variety of databuffering needs, including high speed data acquisition, multipro-cessor interfaces, and communications buffering.These FIFOs have 18-bit input and output ports that arecontrolled by separate clock and enable signals. The input portis controlled by a free-running clock (WCLK) and a write enablepin (WEN). When WEN is asserted, data is written into the FIFOon the rising edge of the WCLK signal. While WEN is held active,data is continually written into the FIFO on each cycle. Theoutput port is controlled in a similar manner by a free-runningread clock (RCLK) and a read enable pin (REN). In addition, theCY7C42X5 have an output enable pin (OE). The read and writeclocks may be tied together for single-clock operation or the twoclocks may be run independently for asynchronous read/writeapplications. Clock frequencies up to 100 MHz are achievable.Retransmit and Synchronous Almost Full/Almost Empty flagfeatures are available on these devices.Depth expansion is possible using the cascade input (WXI, RXI),cascade output (WXO, RXO), and First Load (FL) pins. TheWXO and RXO pins are connected to the WXI and RXI pins ofthe next device, and the WXO and RXO pins of the last deviceshould be connected to the WXI and RXI pins of the first device.The FL pin of the first device is tied to VSS and the FL pin of allthe remaining devices should be tied to VCC.The CY7C42X5 provides five status pins. These pins aredecoded to determine one of five states: Empty, Almost Empty,Half Full, Almost Full, and Full (see Table 2). The Half Full flagshares the WXO pin. This flag is valid in the standalone andwidth-expansion configurations. In the depth expansion, this pinprovides the expansion out (WXO) information that is used tosignal the next FIFO when it will be activated.The Empty and Full flags are synchronous, i.e., they changestate relative to either the read clock (RCLK) or the write clock(WCLK). When entering or exiting the Empty states, the flag isupdated exclusively by the RCLK. The flag denoting Full statesis updated exclusively by WCLK. The synchronous flag archi-tecture guarantees that the flags will remain valid from one clockcycle to the next. As mentioned previously, the AlmostEmpty/Almost FulltheVCC/SMODE is tied to VSS. All configurations are fabricatedusing an advanced 0.65m N-Well CMOS technology. Input ESDprotection is greater than 2001V, and latch-up is prevented bythe use of guard rings.flags become synchronousifCypress Semiconductor CorporationDocument Number: 001-45652 Rev. **
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