DS2141A

DS2141A DS2141A FEATURES

• DS1/ISDN-PRI framing transceiver
• Frames to D4, ESF, and SLC-96 formats
• Parallel control port
• Onboard, dual two-frame elastic store slipbuffers
• Extracts and inserts robbed-bit signaling
• Programmable output clocks
• Onboard FDL support circuitry
• 5V supply; low-power CMOS
• Available in 40-pin DIP and 44-pin PLCC(DS2141Q)
• Compatible with DS2186 Transmit LineInterface, DS2187 Receive Line Interface,DS2188 Jitter Attenuator, DS2290 T1Isolation Stik, and DS2291 T1 Long LoopStik

DS2141A DESCRIPTION

The DS2141A is a comprehensive, software-driven T1 framer. It is meant to act as a slave or coprocessorto a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro tohandle many T1 lines. The DS2141A is very flexible and can be configured into numerous orientationsvia software. The software orientation of the device allows the user to modify their design to conform tofuture T1 specification changes. The controller contains a set of 62 8-bit internal registers which the usercan access. These internal registers are used to configure the device and obtain information from the T11 of 39112099

DS2141A 1.0 INTRODUCTION

The DS2141A T1 Controller has four main sections: the receive side, the transmit side, the line interfacecontroller, and the parallel control port. See the block diagram below. On the receive side, the device willclock in the serial T1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame andmultiframe patterns and establish their respective positions. This information will be used by the rest ofthe receive side circuitry.The DS2141A is an “off-line” framer, which means that all of the T1 serial stream that goes into thedevice will come out of it unchanged. Once the T1 data has been framed to, the robbed-bit signaling dataand FDL can be extracted. The 2-frame elastic stores can either be enabled or bypassed.The transmit side clocks in the unframed T1 stream at TSER and adds in the framing pattern, the robbed-bit signaling, and the FDL. The line interface control port will update line interface devices that contain aserial port. The parallel control port contains a multiplexed address and data structure which can beconnected to either a microcontroller or microprocessor.

DS2141A DS2141A FEATURES

• Parallel control port
• Large error counters
• Onboard dual 2-frame elastic store
• FDL support circuitry
• Robbed-bit signaling extraction and insertion
• Programmable output clocks
• Fully independent transmit and receive sections
• Frame sync generation
• Error-tolerant yellow and blue alarm detection
• Output pin test mode
• Payload loopback capability
• SLC-96 support
• Remote loop up/down code detection
• Loss of transmit clock detection
• Loss of receive clock detection
• 1's density violation detection

DS2141A PIN DESCRIPTION Table 1

SYMBOLTCLKTSERTYPEIIPIN12DS2141ADESCRIPTION3TCHCLKO456-1314TPOSTNEGAD0-AD7BTSOI/OI15161718192021RD (DS)CSALE(AS)WR (R/ W )RLINKVSSRLCLK22RCLKIIIIO-OITransmit Clock. 1.544 MHz primary clock.Transmit Serial Data. Transmit NRZ serial data, sampled on thefalling edge of TCLK.Transmit Channel Clock. 192 kHz clock which pulses high duringthe LSB of each channel. Useful for parallel-to-serial conversion ofchannel data, locating robbed-bit signaling bits, and for blockingclocks in DDS applications. See Section 13 for timing details.Transmit Bipolar Data. Updated on rising edge of TCLK.Address/Data Bus. An 8-bit multiplexed address/data bus.Bus Type Select. Strap high to select Motorola bus timing; straplow to select Intel bus timing. This pin controls the function ofRD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pinsassume the function listed in parentheses ().Read Input (Data Strobe).Chip Select. Must be low to read or write the port.Address Latch Enable (Address Strobe). A positive-going edgeserves to demultiplex the bus.Write Input (Read/Write).Receive Link Data. Updated with either FDL data (ESF) or Fs-bits(D4) or Z-bits (ZBTSI) one RCLK before the start of a frame. SeeSection 13 for timing details.Signal Ground. 0.0 volts.Receive Link Clock. 192 kHz clock which pulses high during theLSB of each channel. Useful for parallel-to-serial conversion ofchannel data, locating robbed-bit signaling bits, and for blockingclocks in DDS applications. See Section 13 for timing details.Receive Clock. 1.544 MHz primary clock.3 of 39

DS2141A clocks in DDS applications. See Section 13 for timing details.