SY89828LHG

SY89828LHG FEATURES

SY89828LHG DESCRIPTION

The SY89828L is a precision fanout buffer with 20differential LVDS (Low Voltage Differential Swing) outputpairs. The part is designed for use in low voltage 3.3Vapplications that require a large number of outputs to driveprecisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (LowVoltage Positive Emitter Coupled Logic) by the CLK_SEL1and CLK_SEL2 pins. The Output Enables (OE1 and OE2)are synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. Thisavoids any chance of generating a runt clock pulse whenthe device is enabled/disabled as can happen with anasynchronous control.The SY89828L features a low pin-to-pin skew of lessthan 50ps—performance previously unachievable in astandard product having such a high number of outputs.The SY89828L is available in a single space saving package,enabling a lower overall cost solution.Primary Clock SourceLVDS_CLKA/LVDS_CLKABackup Clock SourceLVDS_CLKB/LVDS_CLKB100Ω100Ω5555PrimaryCardRedundantCardSEL1Primary/Backup Clock Select(Switchover with 2.0ns)System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application.LVPECL inputs not shown in this application.Precision Edge is a registered trademark of Micrel, [email protected] or (408) 955-16901Rev.: DAmendment: /0Issue Date: January 2008

SY89828LHG APPLICATIONS

■ Enterprise networking■ High-end servers■ Communications

SY89828LHG PIN DESCRIPTIONS

Pin NumberPin Name5, 62, 38, 9I/OInputTypeLVDSLVDS_CLKA/LVDS_CLKALVDS_CLKB/LVDS_CLKBInputLVDSLVPECL_CLKA/LVPECL_CLKAInputLVPECL12, 13LVPECL_CLKB/LVPECL_CLKBInputLVPECL71416111154CLK_SEL1InputCLK_SEL2InputSEL1InputSEL2InputOE1OE2InputInputVCCIPowerLVTTL/CMOSLVTTL/CMOSLVTTL/CMOSLVTTL/CMOSLVTTL/CMOSLVTTL/CMOS17, 32, 40,41, 49, 64VCCOPower10GNDIPower33, 48GNDOPower63, 61, 59, 57, 5553, 51, 47, 45, 43Q0 – Q9OutputLVDS62, 60, 58, 56, 5452, 50, 46, 44, 42/Q0 – /Q9OutputLVDS39, 37, 35, 31, 2927, 25, 23, 21, 19Q10 – Q19OutputLVDSInternalP/U3.5kΩPull-upSee Fig. 23.5kΩPull-upSee Fig. 275kΩpull-downSee Fig. 175kΩpull-downSee Fig. 111kΩPull-up11kΩPull-up11kΩPull-up11kΩPull-up11kΩPull-up11kΩPull-upPrecision Edge®SY89828LPin FunctionDifferential clock input selected by CLK_SEL1, SEL1 andSEL2. Can be left floating if not selected. Floating input, ifselected produces an indeterminate output. Has internal100Ω termination.Differential clock input selected by CLK_SEL1, SEL1 andSEL2. Can be left floating if not selected. Floating input, ifselected produces an indeterminate output. Has internal100Ω termination.Differential clock input selected by CLK_SEL1, SEL1and SEL2. Can be left floating. Floating input, if selectedproduces a LOW at output. Requires external termination.Differential clock input selected by CLK_SEL2, SEL1and SEL2. Requires external termination.Selects LVDS_CLKA input when LOW andLVPECL_CLKA input when HIGH.Selects LVDS_CLKB input when LOW andLVPECL_CLKB input when HIGH.Selects input source CLKA when LOW and CLKBwhen HIGH for outputs Q0 – Q9 and /Q0 – /Q9.Selects input source CLKA when LOW and CLKBwhen HIGH for outputs Q10 – Q19 and /Q10 – /Q19.Enable input synchronized internally to prevent outputglitches or runt pulses.Enable input synchronized internally to prevent outputglitches or runt pulses.Core VCC connected to 3.3V supply. Not connected toVCCO internally. Connected to VCCO on PCB.Bypass with 0.1µF in parallel with 0.01µF low ESRcapacitors as close to VCC pins as possible.Output buffer VCC connected to 3.3V suppy. Not connectedto VCCI internally. Connected to VCCI on PCB.Bypass with 0.1µF in parallel with 0.01µF low ESRcapacitors as close to VCC pins as possible.Core ground not connected to GNDO internally.To be connected to GNDO on PCB.Output buffer ground not connected to GNDI internally.To be connected to GNDI on PCB.Differential clock outputs from CLKA when SEL1 = LOWand from CLKB when SEL1 = HIGH. Q outputs are staticwhen OE1 = LOW. Unused output pair must be terminatedwith 100Ω to maintain low jitter and skew.Differential clock outputs (complement) from CLKA whenSEL1 = LOW and from CLKB when SEL1 = HIGH. /Qoutputs are static HIGH when OE1 = LOW. Unused outputpairs must be externally terminated with 100Ω to maintainlow jitter and skew.Differential outputs from CLKA when SEL2 = LOW andfrom CLKB when SEL2 = HIGH. Q outputs are static LOWwhen OE2 = LOW. Unused output pairs must be externallyterminated with 100Ω to maintain low jitter and [email protected] or (408) 955-16903