AT94K05AL-25AQU

AT94K05AL-25AQU Features

• Monolithic Field Programmable System Level Integrated Circuit (FPSLIC™)– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core,Extensive Data and Instruction SRAM and JTAG ICE
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM– High-performance DSP Optimized FPGA Core Cell– Dynamically Reconfigurable In-System – FPGA Configuration Access AvailableOn-chip from AVR Microcontroller Core to Support Cache Logic® Designs– Very Low Static and Dynamic Power Consumption – Ideal for Portable andHandheld Applications
• Patented AVR Enhanced RISC Architecture– 120+ Powerful Instructions – Most Single Clock Cycle Execution– High-performance Hardware Multiplier for DSP-based Systems– Approaching 1 MIPS per MHz Performance– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers– Low-power Idle, Power-save and Power-down Modes– 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE std. 1149.1 Compliant) Interface– Extensive On-chip Debug Support– Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)
• AVR Fixed Peripherals– Industry-standard 2-wire Serial Interface– Two Programmable Serial UARTs– Two 8-bit Timer/Counters with Separate Prescaler and PWM– One 16-bit Timer/Counter with Separate Prescaler, Compare, CaptureModes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals– AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessibleto FPGA– FPGA Macro Library of Custom Peripherals
• 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks– Two FPGA Clocks Driven from AVR Logic– FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits– Programmable Watchdog Timer with On-chip Oscillator– Oscillator to AVR Internal Clock Circuit– Software-selectable Clock Frequency– Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 3.3V 33 MHz PCI-compliant FPGA I/O– 20 mA Sink/Source High-performance I/O Structures– All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
• 5V I/O Tolerant

AT94K05AL-25AQU Description

The AT94KAL Series FPSLIC family shown in Table 1 is a combination of the popular AtmelAT40K Series SRAM FPGAs and the high-performance Atmel AVR 8-bit RISC microcontrollerwith standard peripherals. Extensive data and instruction SRAM as well as device control andmanagement logic are included on this monolithic device, fabricated on Atmel’s 0.35µ five-layer metal CMOS process.The AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with distributed10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks,Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to 40,000usable gates.Table 1. The AT94K Series CharacteristicsDeviceFPGA GatesFPGA Core CellsFPGA SRAM BitsFPGA Registers (Total)Maximum FPGA User I/OAVR Programmable I/O LinesProgram SRAMData SRAMHardware Multiplier (8-bit)2-wire Serial InterfaceUARTsWatchdog TimerTimer/CountersReal-time ClockJTAG ICETypical AVRthroughputOperatingVoltage(2)AT94K05ALAT94K10ALAT94K40AL5K256204843696810K57640968461441640K2304184322862288164 Kbytes - 16 Kbytes20 Kbytes - 32 Kbytes20 Kbytes - 32 Kbytes4 Kbytes - 16 Kbytes4 Kbytes- 16 Kbytes4 Kbytes - 16 KbytesYesYes2Yes3YesYes(1)YesYes2Yes3YesYesYes2Yes3YesYes(1)19 MIPSYes(1)19 MIPS@ 25 MHz19 MIPSAL3.0 - 3.6V(2)3.0 - 3.6V(2)3.0 - 3.6V(2)Notes:1. FPSLIC parts with JTAG ICE support can be identified by the letter “J” after the device datecode, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Figure 1.2. FPSLIC devices should be laid out during PCB design to support a split power supply.Please refer to the “Designing in Split Power Supply Support for AT94KAL and AT94SALatDevices”http://www.atmel.com/atmel/acrobat/doc2308.pdf.applicationavailableAtmelnote,websitetheon2