AT94S10AL-25DGC

AT94S10AL-25DGC Features

• Multichip Module Containing Field Programmable System Level Integrated Circuit(FPSLIC®) and Secure Configuration EEPROM Memory
• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-SystemProgramming (ISP)
• Field Programmable System Level Integrated Circuit (FPSLIC)– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core andExtensive Data and Instruction SRAM
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM– High-performance DSP Optimized FPGA Core Cell– Dynamically Reconfigurable In-System – FPGA Configuration Access AvailableOn-chip from AVR Microcontroller Core to Support Cache Logic® Designs– Very Low Static and Dynamic Power Consumption – Ideal for Portable andHandheld Applications
• Patented AVR Enhanced RISC Architecture– 120+ Powerful Instructions – Most Single Clock Cycle Execution– High-performance Hardware Multiplier for DSP-based Systems– Approaching 1 MIPS per MHz Performance– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers– Low-power Idle, Power-save, and Power-down Modes– 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE Std. 1149.1 Compliant) Interface– Extensive On-chip Debug Support– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
• AVR Fixed Peripherals– Industry-standard 2-wire Serial Interface– Two Programmable Serial UARTs– Two 8-bit Timer/Counters with Separate Prescaler and PWM– One 16-bit Timer/Counter with Separate Prescaler, Compare, CaptureModes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines DirectlyAccessible to FPGA– FPGA Macro Library of Custom Peripherals
• Up to 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks– Two FPGA Clocks Driven from AVR Logic– FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits– Programmable Watchdog Timer with On-chip Oscillator– Oscillator to AVR Internal Clock Circuit– Software-selectable Clock Frequency– Oscillator to Timer/Counter for Real-time Clock

AT94S10AL-25DGC 1. Description

The AT94S Series (Secure FPSLIC family) shown in Table 1-1 is a combination of the popularAtmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories and the high-per-formance Atmel AVR 8-bit RISC microcontroller with standard peripherals. Extensive data andinstruction SRAM as well as device control and management logic are included in this multi-chipmodule (MCM).The embedded AT40K FPGA core is a fully 3.3V PCI-compliant, SRAM-based FPGA with dis-tributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 globalclocks, Cache Logic ability (partially or fully reconfigurable without loss of data) and 5,000 to40,000 usable gates.Table 1-1.The AT94S Series FamilyDeviceAT94S05ALAT94S10ALAT94S40ALConfiguration Memory Size1 Mbit1 MbitFPGA GatesFPGA Core CellsFPGA SRAM BitsFPGA Registers (Total)Maximum FPGA User I/OAVR Programmable I/O LinesProgram SRAM BytesData SRAM BytesHardware Multiplier (8-bit)2-wire Serial InterfaceUARTsWatchdog TimerTimer/CountersReal-time ClockJTAG ICETypical AVRThroughput5K256204843693810K5764096846137161 Mbit40K2304184322862162164K - 16K4K - 16K20K - 32K4K - 16K20K - 32K4K - 16KYesYes2Yes3YesYesYesYes2Yes3YesYesYesYes2Yes3YesYes@ 25 MHz19 MIPS@ 40 MHz30 MIPS19 MIPS30 MIPS19 MIPS30 MIPSOperating Voltage3.0 - 3.6V3.0 - 3.6V3.0 - 3.6V2