DS92LV1224TMSAX/NOPB

DS92LV1224TMSAX/NOPB Features

n 30–66 MHz Single 1:10 Deserializer with 300–660 Mb/stroughputn Robust Bus LVDS serial data transmission withembedded clock with embedded clock for exceptionalnoise immunity and low EMIn Clock recovery from PLL lock to random data patterns.n Guaranteed transition every data transfer cyclen Low power consumption < 300 mW (typ) @ 66 MHzn Single differential pair eliminates multi-channel skewn Flow-through pinout for easy PCB layoutn Synchronization mode and LOCK indicatorn Programmable edge trigger on clockn High impedance on receiver inputs when power is offn Small 28-lead SSOP package

DS92LV1224TMSAX/NOPB General Description

The DS92LV1224 is a 300 to 660 Mb/s deserializer forhigh-speed unidirectional serial data transmission over FR-4printed circuit board backplanes and balanced coppercables. It receives the Bus LVDS serial data stream from acompatible 10–bit serializer, transforms it back into a 10-bitwide parallel data bus and recovers parallel clock. Thissingle serial data stream simplifies PCB design and reducesPCB cost by narrowing data paths that in turn reduce PCBsize and number of layers. The single serial data stream alsoreduces cable size, the number of connectors, and elimi-nates clock-to-data and data-to-data skew.The DS92LV1224 works well with any National Semiconduc-tor’s Bus LVDS 10–bit serializer within its specified fre-quency operating range. It features low power consumption,and high impedance outputs in power down mode.The DS92LV1224 was designed with the flow-through pinoutand is available in a space saving 28–lead SSOP package.

DS92LV1224TMSAX/NOPB Functional Description

The DS92LV1224 is a 10-bit Deserializer device which to-gether with a compatible serializer (i.e. DS92LV1023E)forms a chipset designed to transmit data over FR-4 printedcircuit board backplanes and balanced copper cables atclock speeds from 30 MHz to 66 MHz.The chipset has three active states of operation: Initializa-tion, Data Transfer, and Resynchronization; and two passivestates: Powerdown and TRI-STATE®.The following sections describe each operation and passivestate.

DS92LV1224TMSAX/NOPB Features

n 30–66 MHz Single 1:10 Deserializer with 300–660 Mb/stroughputn Robust Bus LVDS serial data transmission withembedded clock with embedded clock for exceptionalnoise immunity and low EMIn Clock recovery from PLL lock to random data patterns.n Guaranteed transition every data transfer cyclen Low power consumption < 300 mW (typ) @ 66 MHzn Single differential pair eliminates multi-channel skewn Flow-through pinout for easy PCB layoutn Synchronization mode and LOCK indicatorn Programmable edge trigger on clockn High impedance on receiver inputs when power is offn Small 28-lead SSOP package

DS92LV1224TMSAX/NOPB General Description

The DS92LV1224 is a 300 to 660 Mb/s deserializer forhigh-speed unidirectional serial data transmission over FR-4printed circuit board backplanes and balanced coppercables. It receives the Bus LVDS serial data stream from acompatible 10–bit serializer, transforms it back into a 10-bitwide parallel data bus and recovers parallel clock. Thissingle serial data stream simplifies PCB design and reducesPCB cost by narrowing data paths that in turn reduce PCBsize and number of layers. The single serial data stream alsoreduces cable size, the number of connectors, and elimi-nates clock-to-data and data-to-data skew.The DS92LV1224 works well with any National Semiconduc-tor’s Bus LVDS 10–bit serializer within its specified fre-quency operating range. It features low power consumption,and high impedance outputs in power down mode.The DS92LV1224 was designed with the flow-through pinoutand is available in a space saving 28–lead SSOP package.

DS92LV1224TMSAX/NOPB Functional Description

The DS92LV1224 is a 10-bit Deserializer device which to-gether with a compatible serializer (i.e. DS92LV1023E)forms a chipset designed to transmit data over FR-4 printedcircuit board backplanes and balanced copper cables atclock speeds from 30 MHz to 66 MHz.The chipset has three active states of operation: Initializa-tion, Data Transfer, and Resynchronization; and two passivestates: Powerdown and TRI-STATE®.The following sections describe each operation and passivestate.