TAS5036AIPFC

TAS5036AIPFC Features

•TI PurePath Digital Audio Amplifier
•High-Quality Audio−100-dB SNR−<0.005% THD+N
•Six-Channel Volume Control−Patented Soft Volume−Patented Soft Mute
•16-, 20-, or 24-Bit Input Data
•Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
•Supports Master and Slave Modes
•3.3-V Power Supply Operation
•Economical 80-Pin TQFP Package
•De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
•Clock Oscillator Circuit for Master Modes
•Low-Jitter Internal PLL
•Soft Volume and Mute UpdateEquibit and PurePath Digital are trademarks of Texas Instruments.Other trademarks are the property of their respective owners.Introduction2SLES061B—November 2002—Revised January 2004TAS5036A

TAS5036AIPFC Introduction

The TAS5036A is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-widthmodulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier powerstage, these devices use noise-shaping and sophisticated error-correction algorithms to achieve high powerefficiency and high-performance digital audio reproduction. The TAS5036A is designed to drive up to six digitalpower devices to provide six channels of digital audio amplification. The digital power devices can be sixconventional monolithic power stages (such as the TAS5110) or six discrete differential power stages usinggate drivers and MOSFETs.The TAS5036A has six independent volume controls and mute. The device operates in AD and BD modes.This all-digital audio system contains only two analog components in the signal chain—an LC low-pass filterat each speaker terminal—and can provide up to 96-dB SNR at the speaker terminals. The TAS5036A hasa wide variety of serial input options including right justified (16-, 20-, or 24-bit), I2S (16-, 20-, or 24-bit) leftjustified, and DSP (16-bit) data formats. The device is fully compatible with AES standard sampling rates of44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz, including de-emphasis for 44.1-kHz and 48-kHzsample rates. The TAS5036A plus the TAS51xx power stage device combination was designed for hometheater applications such as DVD minicomponent systems, home theater in a box (HTIB), DVD receiver, A/Vreceiver, or TV sets.1.1Features
•TI PurePath Digital Audio Amplifier
•High-Quality Audio−100-dB SNR−<0.005% THD+N
•Six-Channel Volume Control−Patented Soft Volume−Patented Soft Mute
•16-, 20-, or 24-Bit Input Data
•Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
•Supports Master and Slave Modes
•3.3-V Power Supply Operation
•Economical 80-Pin TQFP Package
•De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
•Clock Oscillator Circuit for Master Modes
•Low-Jitter Internal PLL
•Soft Volume and Mute UpdateEquibit and PurePath Digital are trademarks of Texas Instruments.Other trademarks are the property of their respective owners.Introduction2SLES061B—November 2002—Revised January 2004TAS5036A1.2Functional Block DiagramPWM Ch.Output ControlAVDD_PLLAVSS_PLLVREGA_CAPVREGB_CAPVREGC_CAPDVDD_RCLDVSS_RCLDVDD_PWMDVSS_PWMPower SupplyPLL_FLT_OUTPLL_FLT_RETSCLKLRCLKMCLKOUTSDIN1SDIN2SDIN3MCLK_INXTAL_OUTXTAL_INDBSPDSDASCLCSOPWM_AP_1VALID_1PWM_AP_2VALID_2PWM AP_3VALID_3PWM_AP_4VALID_4PWM_AP_5VALID_5PWM_AP_6VALID_6PWM AM_3PWM_AM_1PWM_AM_2PWM_AM_4PWM_AM_5PWM_AM_6Clock,PLLandSerialDataI/FPDNRESETMUTECLIPERR_RCVYSerialControlI/FReset,Pwr DwnandStatusAuto MuteDe-EmphasisSoft VolumeError RecoverySoft MuteClip DetectSignalProcessingPWMSectionPWM Ch.PWM Ch.PWM Ch.PWM Ch.PWM Ch.M_SDM_SEL1DM_SEL2Introduction3SLES061B—November 2002—Revised January 2004TAS5036A1.3Terminal Assignments22 23VREGB_CAPDVDD_RCLDVSS_RCLDVDD_PWMDVSS_PWMPWM_AP_4PWM_AM_4VALID_4PWM_BM_4PWM_BP_4PWM_AP_5PWM_AM_5VALID_5PWM_BM_5PWM_BP_5PWM_AP_6PWM_AM_6VALID_6PWM_BM_6PWM_BP_66059585756555453525150494847464544434241241234567891011121314151617181920NCNCMCLK_INAVDD_PLLPLL_FLT_OUTPLL_FLT_RETAVSS_PLLNCVREGA_CAPDVSS1NCRESETERR_RCVRYMUTEPDNSDASCLCS0NCNC25 26 27 28PFC PACKAGE(TOP VIEW)80 79 78 77 76 757472 71 707329 30 31 32 3369 682167 66 65 6434 35 36 37 38 39 4063 62 61NC − No internal connectionAVDD_OSCXTL_INXTL_OUTAVSS_OSCDVSSPWM_AP1PWM_AM_1VALID_1PWM_BM_1PWM_BP_1PWM_AP_2PWM_AM_2VALID_2PWM_BM_2PWM_BP_2PWM_AP_3PWM_AM_3VALID_3PWM_BM_3PWM_BP_3NCNCNCDBSPDCLIPSDIN1SDIN2SDIN3MCLK_OUTSCLKLRCLKDVDDDVSSVREGC_CAPDEM_SEL2DEM_SEL1M_SDVSS1DVSS1NCIntroduction4SLES061B—November 2002—Revised January 2004TAS5036A1.4Ordering InformationTexas InstrumentsTASAudio Solutions5036APFCDevice NumberPackage TypeAVAILABLE OPTIONSPACKAGETAPLASTIC 80-PIN TQFP(PFC)0°C to 70°CTAS5036APFC1.5Terminal FunctionsTERMINALFUNCTION†DESCRIPTIONNAMENO.FUNCTION†DESCRIPTIONAVDD_OSC80PAnalog power supply for internal oscillator cellsAVDD_PLL4PAnalog power supply for PLLAVSS_OSC77OAnalog ground for internal oscillator cellsAVSS_PLL7PAnalog ground for PLLCLIP25ODigital clipping indicator, active lowCS018II2C serial control chip address select input, active highDBSPD24ISample rate is double speed (88.2 kHz or 96 kHz), active highDM_SEL136IDe-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)DM_SEL235IDe-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHzDVDD32PDigital power supplyDVDD_PWM57PDigital power supply for PWMDVDD_RCL59PDigital power supply for reclockerDVSS33, 76PDigital ground for digital core and most of I/O buffersDVSS110, 38, 39I/ODigital ground for digital core and most of I/O buffersDVSS_PWM56PDigital ground for PWMDVSS_RCL58PDigital ground for reclockerERR_RCVRY13IError recovery input, active lowLRCLK31I/OSerial audio data left / right clock (sampling rate clock) (input when M_S = 0; output whenM_S = 1)M_S37IMaster/slave mode input signal (master = 1, slave = 0)MCLK_IN3IMCLK input, slave mode (or master / double-speed mode)MCLK_OUT29OMCLK output buffered system clock output if M_S = 1; otherwise set to 0MUTE14IMute input signal, active low (muted signal = 0, normal mode = 1)N/C1, 2, 8, 11,19−23, 40—Not connectedPDN15IPower down, active lowPLL_FLT_OUT5OPLL external filter† I = input; O = output; I/O = input/output; P = powerIntroduction5SLES061B—November 2002—Revised January 2004TAS5036ATERMINALFUNCTION†DESCRIPTIONNAMENO.FUNCTION†DESCRIPTIONPLL_FLT_RET6OPLL external filter (internally connected to AVSS_PLL)PWM_AM_174OPWM 1 output (differential -); {positive H-bridge side}PWM_AM_269OPWM 2 output (differential -); {positive H-bridge side}PWM_AM_364OPWM 3 output (differential -); {positive H-bridge side}PWM_AM_454OPWM 4 output (differential -); {positive H-bridge side}PWM_AM_549OPWM 5 output (differential -); {positive H-bridge side}PWM_AM_644OPWM 6 output (differential -); {positive H-bridge side}PWM_AP_175OPWM 1 output (differential +); {positive H-bridge side}PWM_AP_270OPWM 2 output (differential +); {positive H-bridge side}PWM_AP_365OPWM 3 output (differential +); {positive H-bridge side}PWM_AP_455OPWM 4 output (differential +); {positive H-bridge side}PWM_AP_550OPWM 5 output (differential +); {positive H-bridge side}PWM_AP_645OPWM 6 output (differential +); {positive H-bridge side}PWM_BM_172OPWM 1 output (differential -); {negative H-bridge side}PWM_BM_267OPWM 2 output (differential -); {negative H-bridge side}PWM_BM_362OPWM 3 output (differential -); {negative H-bridge side}PWM_BM_452OPWM 4 output (differential -); {negative H-bridge side}PWM_BM_547OPWM 5 output (differential -); {negative H-bridge side}PWM_BM_642OPWM 6 output (differential -); {negative H-bridge side}PWM_BP_171OPWM 1 output (differential +); {negative H-bridge side}PWM_BP_266OPWM 2 output (differential +); {negative H-bridge side}PWM_BP_361OPWM 3 output (differential +); {negative H-bridge side}PWM_BP_451OPWM 4 output (differential +); {negative H-bridge side}PWM_BP_546OPWM 5 output (differential +); {negative H-bridge side}PWM_BP_641OPWM 6 output (differential +); {negative H-bridge side}RESET12ISystem reset input, active lowSCL17II2C serial control clock inputSCLK30I/OSerial audio data clock (shift clock)SDA16I/OI2C serial control data input/ outputSDIN126ISerial audio data 1 inputSDIN227ISerial audio data 2 inputSDIN328ISerial audio data 3 inputVALID_173OOutput indicating validity of PWM outputs, channel 1, active highVALID_268OOutput indicating validity of PWM outputs, channel 2, active highVALID_363OOutput indicating validity of PWM outputs, channel 3, active highVALID_453OOutput indicating validity of PWM outputs, channel 4, active highVALID_548OOutput indicating validity of PWM outputs, channel 5, active highVALID_643OOutput indicating validity of PWM outputs, channel 6, active highVREGA_CAP9PVoltage regulator capacitorVREGB_CAP60PVoltage regulator capacitorVREGC_CAP34PVoltage regulator capacitorXTL_IN79ICrystal or TTL level clock inputXTL_OUT78OCrystal output (not for external usage)† I = input; O = output; I/O = input/output; P = powerIntroduction6SLES061B—November 2002—Revised January 2004TAS5036AArchitecture Overview7SLES061B—November 2002—Revised January 2004TAS5036A