TAS5036IPFCG4

TAS5036IPFCG4 Features

•True Digital Audio Amplifier
•High Quality Audio–96-dB SNR–<0.1% THD+N
•Six-Channel Volume Control–Patented Soft Volume–Patented Soft Mute
•16-, 20-, or 24-Bit Input Data
•Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
•Supports Master and Slave Modes
•3.3-V Power Supply Operation
•Economical 80-Pin TQFP Package
•De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
•High Power Efficiency
•Clock Oscillator Circuit for Master Modes
•Low Jitter Internal PLL
•Soft Volume and Mute Update
•Excellent PSRREquibit is a trademark of Texas Instruments Incorporated.Introduction2SLES044B—November 2002TAS5036

TAS5036IPFCG4 Introduction

The TAS5036 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse widthmodulator (PWM) based on Equibit technology. Combined with a TI digital amplifier power stage, thesedevices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency andhigh-performance digital audio reproduction. The TAS5036 is designed to drive up to six digital power devicesto provide six channels of digital audio amplification. The digital power devices can be six conventionalmonolithic power stages (such as the TAS5110) or six discrete differential power stages using gate driversand MOSFETs.The TAS5036 has six independent volume controls and mute. It is designed to drive a digital amplifier powerstage (such as the TAS5182) in an H-bridge (bridge tied load) configuration. The device operates in AD andBD modes. This all-digital audio system contains only two analog components in the signal chain—an LClow-pass filter at each speaker terminal and can provide up to 96-dB SNR at the speaker terminals. TheTAS5036 has a wide variety of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or24 bit) left justified, or DSP (16-bit) data formats. The device is fully compatible with AES standard samplingrates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and48-kHz sample rates. The TAS5036 plus the TAS51xx power stage device combination was designed forhome theater applications such as DVD minicomponent systems, home theater in a box (HTIB), DVD receiver,A/V receiver, or TV sets.1.1Features
•True Digital Audio Amplifier
•High Quality Audio–96-dB SNR–<0.1% THD+N
•Six-Channel Volume Control–Patented Soft Volume–Patented Soft Mute
•16-, 20-, or 24-Bit Input Data
•Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
•Supports Master and Slave Modes
•3.3-V Power Supply Operation
•Economical 80-Pin TQFP Package
•De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
•High Power Efficiency
•Clock Oscillator Circuit for Master Modes
•Low Jitter Internal PLL
•Soft Volume and Mute Update
•Excellent PSRREquibit is a trademark of Texas Instruments Incorporated.Introduction2SLES044B—November 2002TAS50361.2Functional Block DiagramPWM Ch.Output ControlAVDD_PLLAVSS_PLLVREGA_CAPVREGB_CAPVREGC_CAPDVDD_RCLDVSS_RCLDVDD_PWMDVSS_PWMPower SupplyPLL_FLT_OUTPLL_FLT_RETSCLKLRCLKMCLKOUTSDIN1SDIN2SDIN3MCLK_INXTAL_OUTXTAL_INCSSSDASCLCSOPWM_AP_1Valid_1PWM_AP_2Valid_2PWM AP_3Valid_3PWM_AP_4Valid_4PWM_AP_5Valid_5PWM_AP_6Valid_6PWM AM_3PWM_AM_1PWM_AM_2PWM_AM_4PWM_AM_5PWM_AM_6Clock,PLLandSerialDataI/FPDNRESETMUTECLIPERR_RCVYSerialControlI/FReset,Pwr DwnandStatusAuto MuteDe-emphasisSoft VolumeError RecoverySoft MuteClip DetectSignalProcessingPWMSectionPWM Ch.PWM Ch.PWM Ch.PWM Ch.PWM Ch.M_SIntroduction3SLES044B—November 2002TAS50361.3Terminal Assignments22 23VREGP_CAPDVDD_RCLDVSS_RCLDVDD_PWMDVSS_PWMPWM_AP_4PWM_AM_4VALID_4PWM_BM_4PWM_BP_4PWM_AP_5PWM_AM_5VALID_5PWM_BM_5PWM_BP_5PWM_AP_6PWM_AM_6VALID_6PWM_BM_6PWM_BP_66059585756555453525150494847464544434241241234567891011121314151617181920NCNCMCLK_INAVDD_PLLPLL_FLT_OUTPLL_FLT_RETAVSS_PLLNCVREGA_CAPDVSS1NCRESETERR_RCVRYMUTEPDNSDASCLCS0NCNC25 26 27 28PAG PACKAGE(TOP VIEW)80 79 78 77 76 757472 71 707329 30 31 32 3369 682167 66 65 6434 35 36 37 38 39 4063 62 61NC – No internal connectionAVDD_OSCXTL_INXTL_OUTAVSS_OSCDVSSPWM_AP1PWM_AM_1VALID_1PWM_BM_1PWM_BP_1PWM_AP_2PWM_AM_2VALID_2PWM_BM_2PWM_BP_2PWM_AP_3PWM_AM_3VALID_3PWM_BM_3PWM_BP_3NCNCNCDBSPDCLIPSDIN1SDIN2SDIN3MCLK_OUTSCLKLRCLKDVDDDVSSVREGC_CAPDEM_SEL2DEM_SEL1M_SDVSS1DVSS1NCIntroduction4SLES044B—November 2002TAS50361.4Ordering InformationTexas InstrumentsTASAudio Solutions5036CPAGDevice NumberTemperature RangePackage TypeAVAILABLE OPTIONSPACKAGETAPLASTIC 80-PIN TQFP(PAG)0°C to 70°CTAS5036CPAG1.5Terminal FunctionsTERMINALI/ODESCRIPTIONNAMENO.I/ODESCRIPTIONAVDD_OSC80PAnalog power supply for internal oscillator cellsAVDD_PLL4PAnalog power supply for PLLAVSS_OSC77AOAnalog ground for internal oscillator cellsAVSS_PLL7PAnalog ground for PLLCLIP25DODigital clipping indicator, active lowCS018DII2C serial control chip address select input, active highDBSPD24DISample rate is double speed (88.2 kHz or 96 kHz), active highDM_SEL136DIDe-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)DM_SEL235DIDe-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHzDVDD32PDigital power supplyDVDD_PWM57PDigital power supply for PWMDVDD_RCL59PDigital power supply for reclockerDVSS33, 76PDigital ground for digital core and most of I/O buffersDVSS110, 38, 39DIODigital ground for digital core and most of I/O buffersDVSS_PWM56PDigital ground for PWMDVSS_RCL58PDigital ground for reclockerERR_RCVRY13DIError recovery input, active lowLRCLK31DIOSerial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when M_S = 1)M_S37DIMaster/slave mode input signal (master = 1, slave = 0)MCLK_IN3DIMCLK input, slave mode (or master / double-speed mode)MCLK_OUT29DOMCLK output buffered system clock output if M_S = 1; otherwise set to 0MUTE14DIMute input signal, active low (muted signal = 0, normal mode = 1)N/C1, 2, 8, 11,19–23, 40Not connectedPDN15DIPower down, active lowIntroduction5SLES044B—November 2002TAS5036TERMINALDESCRIPTIONI/ONAMEDESCRIPTIONI/ONO.PLL_FLT_OUT5AOPLL external filterPLL_FLT_RET6AOPLL external filter (internally connected to AVSS_PLL)PWM_AM_174DOPWM 1 output (differential -); {positive H-bridge side}PWM_AM_269DOPWM 2 output (differential -); {positive H-bridge side}PWM_AM_364DOPWM 3 output (differential -); {positive H-bridge side}PWM_AM_454DOPWM 4 output (differential -); {positive H-bridge side}PWM_AM_549DOPWM 5 output (differential -); {positive H-bridge side}PWM_AM_644DOPWM 6 output (differential -); {positive H-bridge side}PWM_AP_175DOPWM 1 output (differential +); {positive H-bridge side}PWM_AP_270DOPWM 2 output (differential +); {positive H-bridge side}PWM_AP_365DOPWM 3 output (differential +); {positive H-bridge side}PWM_AP_455DOPWM 4 output (differential +); {positive H-bridge side}PWM_AP_550DOPWM 5 output (differential +); {positive H-bridge side}PWM_AP_645DOPWM 6 output (differential +); {positive H-bridge side}PWM_BM_172DOPWM 1 output (differential -); {negative H-bridge side}PWM_BM_267DOPWM 2 output (differential -); {negative H-bridge side}PWM_BM_362DOPWM 3 output (differential -); {negative H-bridge side}PWM_BM_452DOPWM 4 output (differential -); {negative H-bridge side}PWM_BM_547DOPWM 5 output (differential -); {negative H-bridge side}PWM_BM_642DOPWM 6 output (differential -); {negative H-bridge side}PWM_BP_171DOPWM 1 output (differential +); {negative H-bridge side}PWM_BP_266DOPWM 2 output (differential +); {negative H-bridge side}PWM_BP_361DOPWM 3 output (differential +); {negative H-bridge side}PWM_BP_451DOPWM 4 output (differential +); {negative H-bridge side}PWM_BP_546DOPWM 5 output (differential +); {negative H-bridge side}PWM_BP_641DOPWM 6 output (differential +); {negative H-bridge side}RESET12DISystem reset input, active lowSCL17DII2C serial control clock inputSCLK30DIOSerial audio data clock (shift clock)SDA16DIOI2C serial control data input/ outputSDIN126DISerial audio data 1 inputSDIN227DISerial audio data 2 inputSDIN328DISerial audio data 3 inputVALID_173DOOutput indicating validity of PWM outputs, channel 1, active highVALID_268DOOutput indicating validity of PWM outputs, channel 2, active highVALID_363DOOutput indicating validity of PWM outputs, channel 3, active highVALID_453DOOutput indicating validity of PWM outputs, channel 4, active highVALID_548DOOutput indicating validity of PWM outputs, channel 5, active highVALID_643DOOutput indicating validity of PWM outputs, channel 6, active highVREGA_CAP9PC05 voltage regulator capacitorVREGB_CAP60PC05 voltage regulator capacitorVREGC_CAP34PC05 voltage regulator capacitorXTL_IN79AICrystal or TTL level clock inputXTL_OUT78AOCrystal output (not for external usage)Architecture Overview6SLES044B—November 2002TAS5036