Texas Instruments
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• Member of the Texas Instruments Widebus™
•FamilyEPIC™ (Enhanced-Performance ImplantedCMOS) Submicron Process
• Checks Parity
• Able to Cascade With a Second
•
•SN74ALVCH16903ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA PerJESD 17
• Bus Hold on Data Inputs Eliminates the Need
•for External Pullup/Pulldown ResistorsPackage Options Include Plastic 300-milShrink Small-Outline (DL), Thin ShrinkSmall-Outline (DGG), and Thin VerySmall-Outline (DGV) Packages
This 12-bit universal bus driver is designed for 2.3-Vto 3.6-V VCC operation.The SN74ALVCH16903 has dual outputs and canoperate as a buffer or an edge-triggered register. Inboth modes, parity is checked on APAR, whicharrives one cycle after the data to which it applies.The YERR output, which is produced one cycle afterAPAR, is open drain.low,the two data paths. WhenMODE selects one ofMODE isanoperatesdevicetheedge-triggered register. On the positive transition ofthe clock (CLK) input and when the clock-enable(CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition ofCLK and when CLKEN is high, only data set up at the 9A–12A inputs is stored in their internal registers. WhenMODE is high,the A inputs passes directly to the outputs.11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked intothe YERR output register.the device operates as a buffer and data atasWhen used as a single device, parity output enable (PAROE) must be tied high; when parity input/output(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs andPAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When usedin pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nordrive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive buslines without need for interface or pullup components.OE does not affect the internal operation of the device. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74ALVCH16903 is characterized for operation from 0
• C to 70
• C.FUNCTION TABLESFUNCTIONPARITY FUNCTIONPARI/O FUNCTION (1)
TYPE | DESCRIPTION | Select all |
---|---|---|
Current - Output High, Low | 24mA, 24mA | |
Number of Circuits | 12-Bit | |
Logic Type | Universal Bus Driver | |
Product Status | Obsolete | |
Package | Tape & Reel (TR) | |
Series | 74ALVCH | |
Supplier Device Package | 56-SSOP | |
Package / Case | 56-BSSOP (0.295", 7.50mm Width) | |
Mounting Type | Surface Mount | |
Operating Temperature | 0°C ~ 70°C | |
Voltage - Supply | 2.3V ~ 3.6V |
Texas Instruments
Texas Instruments Incorporated (TI) is a global semiconductor powerhouse, crafts advanced analog ICs and embedded processors. Fueled by top-tier minds, TI's innovations drive tech's future, impacting 100,000+ clients.
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