Texas Instruments
Texas Instruments Incorporated (TI) is a global semiconductor powerhouse, crafts advanced analog ICs and embedded processors. Fueled by top-tier minds, TI's innovations drive tech's future, impacting 100,000+ clients.
View All Product from Texas InstrumentsThere is flexible ×9/×18 bus matching on both read and write ports.The period required by the retransmit operation is fixed and short.The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short.These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes.Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) duringthe master-reset cycle.The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFOon every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) andread-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.An output-enable (OE) input is provided for 3-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence.There are no restrictions on the frequency of one clock input with respect to the other.There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode andstandard mode.In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after threetransitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequentwords written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during masterreset determines the timing mode in use.In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless aspecific read operation is performed. A read operation, which consists of activating REN and enabling a risingRCLK edge, shifts the word from internal memory to the data output lines.For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing modepermits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to thecorresponding data inputs of the next). No external logic is required.
TYPE | DESCRIPTION | Select all |
---|---|---|
Programmable | Not Verified | |
FWFT Support | Yes | |
Product Status | Obsolete | |
Retransmit Capability | Yes | |
Programmable Flags Support | Yes | |
Series | 74V | |
Expansion Type | Depth, Width | |
Bus Directional | Uni-Directional | |
Current - Supply (Max) | 35mA | |
Voltage - Supply | 3.15 V ~ 3.45 V | |
Access Time | 5ns | |
Supplier Device Package | 80-LQFP (14x14) | |
Data Rate | 133MHz | |
Package / Case | 80-LQFP | |
Function | Synchronous | |
Mounting Type | Surface Mount | |
Memory Size | 288K (16K x 18)(32K x 9) | |
Operating Temperature | -55°C ~ 125°C | |
Package | Tray |
Texas Instruments
Texas Instruments Incorporated (TI) is a global semiconductor powerhouse, crafts advanced analog ICs and embedded processors. Fueled by top-tier minds, TI's innovations drive tech's future, impacting 100,000+ clients.
View All Product from Texas InstrumentsIC SYNC FIFO MEM 16KX18 80-LQFP
IC SYNC FIFO MEM 4096X18 64-TQFP
IC 32768X36 FIFO MEMORY 128LQFP
FIFO, 64X4, 24NS, ASYNCHRONOUS
IC SYNC FIFO MEM 512X18 64-TQFP
IC MEMORY FIFO 512X18 56-SSOP
IC FIFO REGISTER 4X16 16SOIC
IC SYNC FIFO 65536X18 80QFP
FIFO, 16X5, 75NS, SYNCHRONOUS
FIFO, 256X9, 50NS, ASYNCHRONOUS