SN74V293-6PZA

SN74V293-6PZA

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SN74V293-6PZA
IC SYNC FIFO MEM 65536X18 80LQFP
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$17.98

Quantity Available: 360
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Texas Instruments

Texas Instruments

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SN74V293-6PZA description

The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-infirst-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.There is flexible ×9/×18 bus matching on both read and write ports.The period required by the retransmit operation is fixed and short.The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short.These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes.Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) duringthe master-reset cycle.The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFOon every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) andread-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.An output-enable (OE) input is provided for 3-state control of the outputs.

SN74V293-6PZA description (continued)

The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence.There are no restrictions on the frequency of one clock input with respect to the other.There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode andstandard mode.In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after threetransitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequentwords written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during masterreset determines the timing mode in use.In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless aspecific read operation is performed. A read operation, which consists of activating REN and enabling a risingRCLK edge, shifts the word from internal memory to the data output lines.

Product Attributes

TYPE DESCRIPTION Select all
Programmable Not Verified
FWFT Support Yes
Product Status Active
Retransmit Capability Yes
Programmable Flags Support Yes
Series 74V
Expansion Type Depth, Width
Bus Directional Uni-Directional
Current - Supply (Max) 35mA
Voltage - Supply 3.15 V ~ 3.45 V
Access Time 4.5ns
Supplier Device Package 80-LQFP (14x14)
Data Rate 166MHz
Package / Case 80-LQFP
Function Synchronous
Mounting Type Surface Mount
Memory Size 1.125M (64K x 18)(128K x 9)
Operating Temperature 0°C ~ 70°C
Package Tray

$17.98

Quantity Available: 360
SZC Quality Assurance
Texas Instruments

Texas Instruments

Texas Instruments Incorporated (TI) is a global semiconductor powerhouse, crafts advanced analog ICs and embedded processors. Fueled by top-tier minds, TI's innovations drive tech's future, impacting 100,000+ clients.

View All Product from Texas Instruments
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