TMS320C6455BGTZ

TMS320C6455BGTZ 1 Features

• High-Performance Fixed-Point DSP (C6455)– 1.39-, 1.17-, 1-, 0.83-ns Instruction CycleTime– 720-MHz, 850-MHz, 1-GHz, 1.2-GHz ClockRate– Eight 32-Bit Instructions/Cycle– 9600 MIPS/MMACS (16-Bits)– Commercial Temperature [0°C to 90°C]– Extended Temperature [-40°C to 105°C]
• TMS320C64x+™ DSP Core– Dedicated SPLOOP Instruction– Compact Instructions (16-Bit)– Instruction Set Enhancements– Exception Handling
• TMS320C64x+ Megamodule L1/L2 MemoryArchitecture:– 256K-Bit (32K-Byte) L1P Program Cache[Direct Mapped]– 256K-Bit (32K-Byte) L1D Data Cache[2-Way Set-Associative]– 16M-Bit (2048K-Byte) L2 Unified MappedRAM/Cache [Flexible Allocation]– 256K-Bit (32K-Byte) L2 ROM– Time Stamp Counter
• Enhanced Viterbi Decoder Coprocessor (VCP2)– Supports Over 694 7.95-Kbps AMR– Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)– Supports up to Eight 2-Mbps 3GPP(6 Iterations)– Programmable Turbo Code and DecodingParameters
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface (EMIFA)– Glueless Interface to AsynchronousMemories (SRAM, Flash, and EEPROM) andSynchronous Memories (SBSRAM, ZBTSRAM)– Supports Interface to Standard Sync Devicesand Custom Logic(FPGA, CPLD, ASICs, etc.)– 1.25-, 2.5-, 3.125-Gbps Link Rates– Message Passing, DirectIO Support, ErrorMgmt Extensions, Congestion Control– IEEE 1149.6 Compliant I/Os
• DDR2 Memory Controller– Interfaces to DDR2-533 SDRAM– 32-Bit/16-Bit, 533-MHz (data rate) Bus– 512M-Byte Total Addressable ExternalMemory Space
• EDMA3 Controller (64 Independent Channels)
• 32-/16-Bit Host-Port Interface (HPI)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral ComponentInterconnect (PCI) Master/Slave InterfaceConforms to PCI Local Bus Specification (v2.3)
• One Inter-Integrated Circuit (I2C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)– IEEE 802.3 Compliant– Supports Multiple Media IndependentInterfaces (MII, GMII, RMII, and RGMII)– 8 Independent Transmit (TX) and8 Independent Receive (RX) Channels
• Two 64-Bit General-Purpose Timers,Configurable as Four 32-Bit Timers
• UTOPIA– UTOPIA Level 2 Slave ATM Controller– 8-Bit Transmit and Receive Operations up to50 MHz per Direction– User-Defined Cell Format up to 64 Bytes
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller
• Secondary PLL and PLL Controller, Dedicatedto EMAC and DDR2 Memory Controller
• Advanced Event Triggering (AET) Compatible
• Trace-Enabled Device
•IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
• 697-Pin Ball Grid Array (BGA) Package(CTZ, GTZ, or ZTZ Suffix), 0.8-mm Ball Pitch
• 0.09-μm/7-Level Cu Metal Process (CMOS)
• 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os,– 32M-Byte Total Addressable External1.25-/1.2-V InternalMemory Space
• Four 1x Serial RapidIO® Links (or One 4x),v1.2 Compliant

TMS320C6455BGTZ 1.2 Description

The TMS320C64x+™ DSPs (including the TMS320C6455 device) are the highest-performance fixed-pointDSP generation in the TMS320C6000™ DSP platform. The C6455 device is based on the third-generationhigh-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed byTexas Instruments (TI), making these DSPs an excellent choice for applications including video andtelecom infrastructure,imaging/medical, and wireless infrastructure (WI). The C64x+™ devices areupward code-compatible from previous devices that are part of the C6000™ DSP platform.Based on 90-nm process technology and with performance of up to 9600 million instructions per second(MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effectivesolutions to high-performance DSP programming challenges. The C6455 DSP possesses the operationalflexibility of high-speed controllers and the numerical capability of array processors.The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlierC6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doublesthe multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates(MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, eachmultiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clockcycle.The TCI6482 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improvessystem performance and reduces system cost for applications that include multiple DSPs on a board,such as video and telecom infrastructures and medical/imaging.