TMS320C6727ZDH300

TMS320C6727ZDH300 1.1 Features

• C672x: 32-/64-Bit 300-MHz Floating-Point DSPs
• Upgrades to C67x+ CPU From C67x™ DSPGeneration:– 2X CPU Registers [64 General-Purpose]– New Audio-Specific Instructions– Compatible With the C67x CPU
• Enhanced Memory System– 256K-Byte Unified Program/Data RAM– 384K-Byte Unified Program/Data ROM– Single-Cycle Data Access From CPU– Large Program Cache (32K Byte) SupportsRAM, ROM, and External Memory
• External Memory Interface (EMIF) Supports– 100-MHz SDRAM (16- or 32-Bit)– Asynchronous NOR Flash, SRAM (8-,16-, or32-Bit)– NAND Flash (8- or 16-Bit)
• Enhanced I/O System– High-Performance Crossbar Switch– Dedicated McASP DMA Bus– Deterministic I/O Performance
• dMAX (Dual Data Movement Accelerator)Supports:– 16 Independent Channels– Concurrent Processing of Two TransferRequests– 1-, 2-, and 3-DimensionalMemory-to-Memory andMemory-to-Peripheral Data Transfers– Circular Addressing Where the Size of aCircular Buffer (FIFO) is not Limited to 2n– Table-Based Multi-Tap Delay Read andWrite Transfers From/To a Circular Buffer
• Three Multichannel Audio Serial Ports– Transmit/Receive Clocks up to 50 MHz– Six Clock Zones and 16 Serial Data Pins– Supports TDM, I2S, and Similar Formats– DIT-Capable (McASP2)
• Universal Host-Port Interface (UHPI)– 32-Bit-Wide Data Bus for High Bandwidth– Muxed and Non-Muxed Address and Data
• Two 10-MHz SPI Ports With 3-, 4-, and 5-PinOptions
• Two Inter-Integrated Circuit (I2C) Ports
• Real-Time Interrupt Counter/Watchdog
• Oscillator- and Software-Controlled PLL
• Applications:– Professional Audio
• Mixers
• Effects Boxes
• Audio Synthesis
•
• Audio Conferencing
• Audio Broadcast
• Audio EncoderInstrument/Amp Modeling– Emerging Audio Applications– Biometrics– Medical– Industrial
• Commercial or Extended Temperature
• 144-Pin, 0.5-mm, PowerPAD™ Thin QuadFlatpack (TQFP) [RFP Suffix]
• 256-Terminal, 1.0-mm, 16x16 Array Plastic BallGrid Array (PBGA) [GDH and ZDH Suffixes]

TMS320C6727ZDH300 1.2 Description

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance32-/64-bitfloating-point digital signal processors. The TMS320C672x includes the TMS320C6727,TMS320C6726, and TMS320C6722 devices. (1)Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671xDSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, andfloating-point performance per clock cycle. At 300 MHz, the CPU is capable of a maximum performance ofinstructions (six of which are floating-point2400 MIPS/1800 MFLOPS by executing up to eightinstructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precisionfloating-point, and 64-bit double-precision floating-point arithmetic.Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byteROM as unified program/data memory. Development is simplified since there is no fixed division betweenprogram and data memory size as on some other devices.The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.Up to three parallel accesses to the internal RAM and ROM from three of the following four sources aresupported:
• Two 64-bit data accesses from the C67x+ CPU
• One 256-bit program fetch from the core and program cache
• One 32-bit data access from the peripheral system (either dMAX or UHPI)The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents mostprogram/data access conflicts to the on-chip memory. It also enables effective program execution from anoff-chip memory such as an SDRAM.High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub betweenthe different bus masters (CPU, dMAX, UHPI) and differenttargets (peripherals and memory). Thecrossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheralconnections).Multiple transfers occur in parallel through the crossbar as long as there is no conflict between busmasters for a particular target. When a conflict does occur, the arbitration is a simple and deterministicfixed-priority scheme.The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followednext by the UHPI, and finally by the CPU.dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data MovementAcceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfersbetween the internal data memory controller and the device peripherals on the C672x DSPs. The dMAXallows movement of data to/from any addressable memory space including internal memory, peripherals,and external memory.The dMAX controller includes features such as the capability to perform three-dimensional data transfersfor advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFOwith delay-tap based reading and writing of data. The dMAX controller is capable of concurrentlyprocessing two transfer requests (provided that they are to/from different source/destinations).External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on theC672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF datawidth is 16 bits wide on the C6726 and C6722, and 32 bits wide on the C6727.SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.The C6726 and C6722 support SDRAM devices up to 128M bits.