TMS320C6748EZCE3

TMS320C6748EZCE3 Features

• 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP
• C674x Instruction Set Features– Superset of the C67x+ and C64x+ ISAs– Up to 3648 MIPS and 2746 MFLOPS– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)– 8-Bit Overflow Protection– Bit-Field Extract, Set, Clear– Normalization, Saturation, Bit-Counting– Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture– 32KB of L1P Program RAM/Cache– 32KB of L1D Data RAM/Cache– 256KB of L2 Unified Mapped RAM/Cache– Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3(EDMA3):– 2 Channel Controllers– 3 Transfer Controllers– 64 Independent DMA Channels– 16 Quick DMA Channels– Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core– Load-Store Architecture With NonalignedSupport– 64 General-Purpose Registers (32-Bit)– Six ALU (32- and 40-Bit) Functional Units– Supports 32-Bit Integer, SP (IEEE SinglePrecision/32-Bit) and DP (IEEE DoublePrecision/64-Bit) Floating Point– Supports up to Four SP Additions Per Clock,Four DP Additions Every Two Clocks– Supports up to Two Floating-Point (SP or DP)Reciprocal Approximation (RCPxP) andSquare-Root Reciprocal Approximation(RSQRxP) Operations Per Cycle– Two Multiply Functional Units:– Mixed-Precision IEEE Floating-Point MultiplySupported up to:– 2 SP × SP → SP Per Clock– 2 SP × SP → DP Every Two Clocks– 2 SP × DP → DP Every Three Clocks– 2 DP × DP → DP Every Four Clocks– Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, orEight 8 × 8-Bit Multiplies per Clock Cycle,and Complex Multiples– Instruction Packing Reduces Code Size– All Instructions Conditional– Hardware Support for Modulo Loop Operation– Protected Mode Operation– Exceptions Support for Error Detection andProgram Redirection
• Software Support– TI DSP BIOS™– Chip Support Library and DSP Library
• 128KB of RAM Shared Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB andDDR2 Interfaces)
• Two External Memory Interfaces:– EMIFA– NOR (8- or 16-Bit-Wide Data)– NAND (8- or 16-Bit-Wide Data)– 16-Bit SDRAM With 128-MB Address Space– DDR2/Mobile DDR Memory Controller With oneof the Following:– 16-Bit DDR2 SDRAM With 256-MB AddressSpace– 16-Bit mDDR SDRAM With 256-MB AddressSpace
• Three Configurable 16550-Type UART Modules:– With Modem Control Signals– 16-Byte FIFO– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each WithMultiple Chip Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)Card Interfaces With Secure Data I/O (SDIO)Interfaces
• Two Master and Slave Inter-Integrated Circuits(I2C Bus™)

TMS320C6748EZCE3 1.3 Description

TMS320C6748
• Machine Vision (Low-End)The TMS320C6748 fixed- and floating-point DSP is a low-power applications processor based on a C674xDSP core. This DSP provides significantly lower power than other members of the TMS320C6000™platform of DSPs.The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)to quickly bring to market devices with robust operating systems, rich user interfaces, and high processorperformance through the maximum flexibility of a fully integrated, mixed processor solution.The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache.The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between programand data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM sharedmemory is available for use by other hosts without affecting DSP performance.For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual propertyand prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust," the secure boot flow ensures a known good starting point for code execution. Bydefault, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG portcan be enabled during the secure boot process during application development. The boot modules areencrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted andauthenticated when loaded during secure boot. Encryption and decryption protects customers’ IP and letsthem securely set up the system and begin device operation with known, trusted code.Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic SecureBoot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryptionscheme which not only protects the boot process but also offers the ability to securely upgrade boot andapplication software code. A 128-bit device-specific cipher key, known only to the device and generatedusing a NIST-800-22 certified random number generator, is used to protect customer encryption keys.When an update is needed, the customer uses the encryption keys to create a new encrypted image.Then the device can acquire the image through an external interface, such as Ethernet, and overwrite theexisting code. For more details on the supported security features or TI’s Basic Secure Boot, see theTMS320C674x/OMAP-L1x Processor Security User’s Guide.(McASP) with 16 serializers and FIFO buffers;The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a managementdata input/output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two I2C Businterfaces; one multichannel audio serial porttwomultichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) withfour 64-bit general-purpose timers each configurable (one configurable as amultiple chip selects;watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output(GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes,multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) moduleperipherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memoryinterfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories orperipherals; and a higher speed DDR2/Mobile DDR controller.The EMAC provides an efficient interface between the device and a network. The EMAC supports both10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, anMDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

TMS320C6748EZCE3 1.2 Applications

• Currency Inspection
• Biometric Identification