TMS320C6655SCZH

The C665xare high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicorearchitecture. Incorporating the new and innovative C66x DSP core, this device can run at a corespeed of up to 1.25 GHz. For developers of a broad range of applications, bothC665x DSPs enable aplatform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with allexisting C6000 family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating varioussubsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses severalinnovative components and techniques to maximize intradevice and interdevice communication thatlets the various DSP resources operate efficiently and seamlessly. Central to this architecture arekey components such as Multicore Navigator that allows for efficient data management between thevarious device components. The TeraNet is a nonblocking switch fabric enabling fast andcontention-free internal data movement. The multicore shared memory controller allows access toshared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability ofC64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core rawcomputational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precisionfloating-point MAC operations per cycle and can perform double- and mixed-precision operations andis IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core)targeted for floating-point and vector math oriented processing. These enhancements yield sizeableperformance improvements in popular DSP kernels used in signal processing, mathematical, and imageacquisition functions. The C66x core is backward code-compatible with TI’s previous generationC6000 fixed- and floating-point DSP cores, ensuring software portability and shortened softwaredevelopment cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KBof L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache.The device also integrates 1024KB of Multicore Shared Memory that can beused as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detectionand error correction. For fast access to external memory, this device includes a 32-bit DDR-3external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART,Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronousEMIF, along with general-purpose CMOS IO. For high throughput, low latencycommunication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink isincluded.

The C665xdevices have a complete set of development tools, which includes: an enhanced C compiler, anassembly optimizer to simplify programming and scheduling, and a Windows debugger interface forvisibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performancestructure for integrating RISC and DSP cores with application-specific coprocessors and I/O. TheKeyStone architecture is the first of its kind that provides adequate internal bandwidth fornonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internalbandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, MulticoreShared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues.When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatchthat directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC)uses the two Tbps capacity of the TeraNet switched central resource to move packets. The MulticoreShared Memory Controller lets processing cores access shared memory directly without drawing fromthe capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCswork in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interfacefor chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks totandem devices transparently and executes tasks as if they are running on local resources.

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