EPF6024AQC240-1

Features

■ Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes during prototyping or design testing 

■ Product features 

– Register-rich, look-up table- (LUT-) based architecture 

– OptiFLEX® architecture that increases device area efficiency 

– Typical gates ranging from 5,000 to 24,000 gates (see Table 1) 

– Built-in low-skew clock distribution tree 

– 100% functional testing of all devices; test vectors or scan chains are not required 

■ System-level features 

– In-circuit reconfigurability (ICR) via external configuration device or intelligent controller 

– 5.0-V devices are fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 

– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic 

– MultiVoltTM I/O interface operation, allowing a device to bridge between systems operating at different voltages 

– Low power consumption (typical specification less than 0.5 mA in standby mode) 

– 3.3-V devices support hot-socketing

■ Powerful I/O pins

– Individual tri-state output enable control for each pin 

– Programmable output slew-rate control to reduce switching noise 

– Fast path from register to I/O pin for fast clock-to-output time 

■ Flexible interconnect 

– FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays 

– Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) 

– Dedicated cascade chain that implements high-speed, high-fanin logic functions (automatically used by software tools and megafunctions) 

– Tri-state emulation that implements internal tri-state networks 

– Four low-skew global paths for clock, clear, preset, or logic signals 

■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 

■ Flexible package options 

– Available in a variety of packages with 100 to 256 pins, including the innovative FineLine BGATM packages (see Table 2) 

– SameFrameTM pin-compatibility (with other FLEX® 6000 devices) across device densities and pin counts 

– Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and ball-grid array (BGA) packages (see Table 2) 

– Footprint- and pin-compatibility with other FLEX 6000 devices in the same package 

■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules (LPM), Verilog HDL, VHDL, DesignWare components, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

General Description

The Altera® FLEX 6000 programmable logic device (PLD) family provides a low-cost alternative to high-volume gate array designs. FLEX 6000 devices are based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The devices have reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. Designers can also change functionality during operation via in-circuit reconfiguration. 

FLEX 6000 devices are reprogrammable, and they are 100% tested prior to shipment. As a result, designers are not required to generate test vectors for fault coverage purposes, allowing them to focus on simulation and design verification. In addition, the designer does not need to manage inventories of different gate array designs. FLEX 6000 devices are configured on the board for the specific functionality required. 

Table 3 shows FLEX 6000 performance for some common designs. All performance values shown were obtained using Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.

Feature