SN74LVC823ADWR

SN74LVC823ADWR

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SN74LVC823ADWR
IC FF D-TYPE SNGL 9BIT 20SOIC
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SN74LVC823ADWR Products

This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC823ADWR is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock.

A buffered output-enable (OE)\ input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Feature

  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 7.9 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)    >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Product Attributes

TYPE DESCRIPTION Select all
Number of Elements 1
Output Type Tri-State, Non-Inverted
Package / Case 24-SOIC (0.295", 7.50mm Width)
Type D-Type
Supplier Device Package 24-SOIC
Input Capacitance 5 pF
Function Master Reset
Mounting Type Surface Mount
Current - Quiescent (Iq) 10 µA
Product Status Obsolete
Operating Temperature -40°C ~ 85°C (TA)
Package Tape & Reel (TR)
Voltage - Supply 1.65V ~ 3.6V
Series 74LVC
Current - Output High, Low 24mA, 24mA
Trigger Type Positive Edge
Max Propagation Delay @ V, Max CL 8ns @ 3.3V, 50pF
Clock Frequency 150 MHz
Number of Bits per Element 9

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Price negotiable

Price update:a months ago
Available in stock: 4746
Texas Instruments

Texas Instruments

Texas Instruments Incorporated (TI) is a global semiconductor powerhouse, crafts advanced analog ICs and embedded processors. Fueled by top-tier minds, TI's innovations drive tech's future, impacting 100,000+ clients.

View All Product from Texas Instruments

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