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XC17V04PC20C Xilinx
Xilinx
Xilinx stands as a preeminent purveyor of All Programmable Field-Programmable Gate Arrays (FPGAs), System on Chips (SoCs), Multiprocessor System on Chips (MPSoCs), and Three-Dimensional Integrated Circuits (3D ICs). AMD stands in a distinctive position, facilitating applications that embody a dual nature of software-defined sophistication and hardware-honed optimization. This empowering of industries finds its zenith in the realms of Cloud Computing, 5G Wireless Connectivity, Embedded Vision, and the sprawling domain of Industrial Internet of Things (IIoT).
View All Product from XilinxXilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, costeffective method for storing large Xilinx FPGA configuration bitstreams. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1 and Figure 2 for simplified block diagrams of the XC17V00 family.
The XC17V00 PROM can configure a Xilinx FPGA using the FPGA serial configuration mode interface. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.
The XC17V08(1) and XC17V16 PROM can optionally configure a Xilinx FPGA using the FPGA Parallel (SelectMAP) configuration mode interface. When the FPGA is in Master SelectMAP mode, the FPGA generates the configuration clock that drives the PROM.
When the FPGA is in Slave SelectMAP mode, an external, free-running oscillator generates the configuration clock that drives the PROM and the FPGA. After the rising configuration clock (CCLK) edge, data is available on the PROMs DATA (D0-D7) pins. The data is clocked into the FPGA on the following rising edge of the CCLK (Figure 3).
Multiple PROMs can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family.
For device programming, either the Xilinx ISE Foundation or ISE WebPACK software compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
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Mfr Part # | Price ($) | Quantity Available | |
---|---|---|---|
XC17V02VQ44IIC PROM SER 2MBIT 3.3V 44-VQFP | 2.76 |
3989
Marketplace | |
XC17V01VO8IIC PROM SER 1M 8-SOIC | 5.51 |
3075
Marketplace |
TYPE | DESCRIPTION | Select all |
---|---|---|
Supplier Device Package | 20-PLCC (9x9) | |
Package | Tube | |
Product Status | Obsolete | |
Programmable | Not Verified | |
Programmable Type | OTP | |
Memory Size | 4Mb | |
Voltage - Supply | 3V ~ 3.6V | |
Operating Temperature | 0°C ~ 70°C | |
Mounting Type | Surface Mount | |
Package / Case | 20-LCC (J-Lead) |
Xilinx
Xilinx stands as a preeminent purveyor of All Programmable Field-Programmable Gate Arrays (FPGAs), System on Chips (SoCs), Multiprocessor System on Chips (MPSoCs), and Three-Dimensional Integrated Circuits (3D ICs). AMD stands in a distinctive position, facilitating applications that embody a dual nature of software-defined sophistication and hardware-honed optimization. This empowering of industries finds its zenith in the realms of Cloud Computing, 5G Wireless Connectivity, Embedded Vision, and the sprawling domain of Industrial Internet of Things (IIoT).
View All Product from XilinxCONFIG MEMORY, 2MX1, SERIAL
IC PROM SRL FOR 4M GATE 44-VQFP
IC PROM SER I-TEMP 3.3V 8-SOIC
IC 3V SER CFG PROM 256K 8-SOIC
IC PROM SER C-TEMP 36K 20-PLCC
IC PROM SER C-TEMP 3.3V 8-SOIC
CONFIG MEMORY, 1M BITS, SERIAL
IC PROM SERIAL 65K 8-SOIC
IC PROM SER 200000 I-TEMP 44VQFP
IC SERIAL CFG PROM 256K 20-PLCC